The following list gives a glimpse of the ongoing projects in my research lab, Embedded Systems Laboratory (ESL). While focusing on the actual research, we have not yet created fancy web page with all the cool information. Nonetheless, please find here at least a glimpse of what is going on.

The overarching goal of our research is improving the design of embedded systems that contain both hardware and software. We focus on system-level research that jointly addresses both hardware and software aspects.


Holistic Design Methodology for Automated Implementation of Human-in-the-Loop Cyber-Physical Systems

This project develops a framework for design automation of cyber-physical systems to augment human interaction with complex systems that integrate across computational and physical environments. As a design driver, the project develops a Body/Brain Computer Interface (BBCI) for the population of functionally locked-in individuals, who are unable to interact with the physical world through movement and speech. The BBCI will enable communication with other humans through expressive language generation and interaction with the environment through robotic manipulators.

This multi-university project is supported by the National Science Foundation under Grant No. 1136027.


Versatile Onboard Traffic Embedded Roaming Sensors

The VOTERS (Versatile Onboard Traffic-Embedded Roaming Sensors) project provides a framework to complement periodical localized inspections of roadways and bridge decks with continuous network-wide health monitoring. Utilizing traffic-embedded Vehicles Of Opportunity (VOOs) roaming through daily traffic eliminates hazardous, congestion-prone work zones, that are typically set up to gather these critical inspection data sets. It also provides maintenance decision makers and researchers with a temporal and spatial data set not available in roadway and bridge deck inspection today.
Realizing a Roaming Multi-Modal Multi-Sensor System poses nice challenges for the distributed embedded real-time system design. Large amounts of data need to be processed, heterogenous processing nodes need to communicate with each other, strict time synchronization is necessary to correlate data from separate sensors and finally sensor fusion is needed to construct a coherent view merging the data from separate sensors.

This multi-university project is funded by NIST under the TIP program.


Designing Green Software for High Performance Computing Clusters

Our research goal is to design systematic, inexpensive methods to optimize the application SW for reducing the energy consumed per useful work done, thus increasing the energy efficiency. We observe that in HPC software, communication and data sharing among the threads of an application are critical factors affecting performance and energy. Therefore, we specifically target analyzing and optimizing these aspects. We plan to demonstrate proof-of-concept of the proposed techniques using parallel benchmarks and a real-life HPC application, Molecular Dynamics (MD).
This project is seed funded by the Massachusetts Green High-Performance Computing Center (MGHPCC).


System-Level Design Principles Market-oriented SoC

Architecting Multi-Processor System-on-Chip (MPSoC) solutions for multiple markets with many applications has appeared as an important trend. This allows to focus development efforts onto designing solutions that are applicable to a broad market (thus recuperating initial development cost), yet are designed specifically for the market (thus having performance / power advantages). In this project, we are looking into design methodologies for Market-oriented MP-SoCs pushing the abstraction envelope, we look at architectural support to efficiently execute a set of applications from the same market. As a driving factor, we look into the Embedded Vision market.

This project is funded by Analog Devices Inc. link


Hardware / Software Co-Design Using Simulink

Meeting the stringent performance, power and cost requirements of modern embedded systems requires students to gain competencies in system design such as architecture, partitioning, profiling and tradeoffs using platforms composed of user-definable software and configurable hardware. Exploring the large design space (containing a plethora of HW/SW alternatives) toward an efficient solution not only requires detailed hardware architecture and software design knowledge, it moreover requires integrated system design skills spanning horizontally across HW/SW as well as vertically across abstraction levels in the execution stack.
The overarching goal of this project is to utilize the model-based design approach of Matlab/Simulink for hardware/software codesign. For that we integrate the capabilities of Simulink Embedded Coder for generating software and Simulink HDL Coder for synthesizing hardware (mapped to an FPGA), with our custom communication synthesis. We target execution on a DSP / FPGA platform (link).

This project is funded by Mathworks


Bridging Algorithm and System-Level Design

System-Level Design Environments (SLDEs) are often utilized for tackling the design complexity of modern embedded systems. SLDEs typically start with a specification capturing core algorithms. Algorithm development itself largely occurs in Algorithm Design Environments (ADE) with little or no hardware concern. Currently, algorithm and system design environments are disjoint; system level specifications are manually implemented which leads to the specification gap.

In this research, we bridge algorithm and system design environments creating a
unified design flow facilitating algorithm and system co-design. It enables algorithm realizations over heterogeneous platforms, while still tuning the algorithm according to platform needs. Our design flow starts with algorithm design in Simulink, out of which a System Level Design Language (SLDL)-based specification is synthesized. This specification then is used for design space exploration across heterogeneous target platforms and abstraction levels, and, after identifying a suitable platform, synthesized to HW/SW implementations. It realizes a unified development cycle across algorithm modeling and
system-level design with quick responses to design decisions on algorithm-, specification- and system exploration level. It empowers the designer to combine analysis results across environments, apply cross layer optimizations, which will yield an overall optimized design through rapid design iterations. synthesize SLDL out of Simulink for heterogeneous multi-core exploration.


Cross Layer Optimizations for Processors with Large Register Files

Modern embedded processors increasingly utilize larger register files. While large register files improve performance, reducing accesses to the memory hierarchy, they also have a considerable contribution in processor static power and a significant contribution to embedded processors reliability. At the same time, not all registers are used in all applications. However, the processor core itself is not aware of register utilization and in particular cannot predict if a register will be read in the future (ie. is active), or will be written to in the future (ie. is passive). This line of research introduces cross layer optimizations that utilize application binary analysis, instrumentation, and execution on an improved architecture. This offers opportunity to reduce static power consumption, and improving reliability of register files.


Personal Active Learning (PAL)

The goal of this project to integrate an active learning platform into the Northeastern University undergraduate ECE curriculum. The main goals of this effort will be:

Integrating a common active learning platform will have a multitude of benefits:

This project is sponsored by Analog Devices and The House Foundation.


Embedded Software Development in a System Level Design Context

System level design is one approach to tackle the complexity of designing a modern System-on-Chip. One major aspect is the capability of developing the system model without a special attention to the later occurring hardware software split. Both hardware and software can be developed seamlessly at the same time. It therefore allows a better integration between those traditionally separated development flows.
Simulated Bandwidth of models at different levels of abstraction.
Hardware / software co-simulation is needed for an efficient integrated HW/SW development. Depending on the design phase this co-simulation can be done at different levels of abstraction. They range from the very abstract simulation at the specification level down to the cycle accurate simulation of hardware and the software execution on an instruction set simulator.

The goals of this project address two separate aspects. For one, we want to abstractly model software the software execution environment. In addition, we want to automatically create all embedded software out of an abstract system model.

For the modeling part, we create abstract processor models at varying level of abstraction. We seek to identify essential features for processor modeling that yield sufficiently timing accurate results in an acceptable simulation time. Due to the wide popularity of the ARM processors (and our availability of the AMBA AHB bus models), we have chosen an instruction set simulator (SWARM) for the ARM7TDMI. We integrated the ISS into the System-on-Chip Design Environment (SCE), which allows us to quickly generate cycle accurate models of custom SoC architectures. We have integrated a real-time operating system (MicroC/OS-II by Micrium) to run on top of the ISS. This gives us the ability to explore the real-time implications of the software hardware interaction.

We have also developed a tool that automatically generates - based on the abstract model in the SLDL - the embedded software and targets the code to a chosen RTOS. This generation includes, code generation (generating software code inside each task), communication synthesis (creating drivers for internal and external communication), multi-task synthesis (targeting toward an existing RTOS, or converting to state-machine interrupt-based multi-tasking), and finally the binary creation that compiles and links everything together into a the final execution binary.

Relevant publications for the modeling aspect:

Relevant publications for the synthesis aspect:


Result Oriented Modeling

Despite our optimistic title of the previous project "FAT: Fast and Accurate TLM", we analyzed TLMs for many different bus systems and quantified the TLM trade-off between speed and accuracy. A model is either fast or accurate for the general case (although there are cases where a TLM is accurate enough).

Now, we introduced ROM: Result Oriented Modeling, ROM principle, optimistic prediction, check for disturbing influence and prediction update.a modeling technique communication TLMs. ROM can eliminate the inaccuracies for TLM in many cases, yet it is able to retain the TLM speed advantage. ROM makes the assumption that an application only needs to observe the timing at a transaction boundary. On the other hand, everything inside the transaction is hidden.

With this assumption, ROM can rearrange or omit internal states to gain speed. Instead of simulating each bus cycle, ROM makes and optimistic prediction right at the beginning of the transaction. It uses calculates the transaction duration (Answering: How long will this transaction take, if there is no further preemption?). Then, at the end of the predicted time, it checks weather the assumptions did hold true. It updates the prediction, in case there was an unexpected preemption. With that ROM reaches both: speed and accuracy.

Relevant publications:

Fast and Accurate Transaction-Level Modeling

The field of embedded systems increasingly extends to more complex scenarios including safety critical systems. Distributed embedded real-time systems with many processors become necessary. Accurate communication modeling is an important issue for the design of those complex systems. However, efficient system level design requires also high execution performance especially for communication models.
Simulated Bandwidth of models at different levels of abstraction.
Recent research work introduced Transaction Level Modeling as a means of increasing the simulation performance. Here, large speed-up is gained by abstracting away communication details. Inevitably this results in a loss of simulation accuracy. However, due to the complexity of accuracy measurements and its statistical analysis, no clear expressive quantification of the speed-accuracy tradeoff prevails.

The goals of this research project include:

Relevant publications: